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Design Space Exploration or Design Space Denial?

For a decade, AI silicon design converged on one comfortable target. Agentic and physical AI are breaking that convergence — and it's worth asking honestly whether we're still exploring the design space, or just getting good at exploring the same corner of it.

Download the ESSERC 2026 keynote (PDF)39 slides · 52nd IEEE ESSERC, Palma · 10 September 2026

For a decade, AI silicon design has converged on one comfortable target: transformer inference and training, optimised above all for data-centre throughput.

That convergence wasn’t unreasonable. It followed the workloads that mattered most, for as long as those workloads stayed roughly the same shape. They no longer do. Agentic AI — long-running, tool-using, multi-step, latency-sensitive — and physical AI — edge-deployed, power-constrained, safety-critical — are exposing cracks in a decade of assumptions that most current design-space-exploration tooling was never built to surface.

So here’s the questions I want to put to anyone building chips, systems, or infrastructure for AI right now: are we still exploring the design space, or have we just gotten very good at exploring the same comfortable corner of it? , ** How much we can continue the AI race by increasing power and compute resources without considering social and ambiental impact? ** , and .. ** how about other fundamental principles on how we design systems considering other aspects such as safety and privacy? **

This is the opening post in a series where I’ll try to answer that question properly — not with a slogan, but with data, with named standards, and with an honest account of where the industry’s own claims don’t yet hold up. This week at ESSERC 2026, I did gave a first keynote where I tried to outline some of the principales that in my modest opinion we need to do carrion to perform a more human centric AI Intelligence. A longer position paper will follow it. Over the next several posts I’ll walk through what I think are the four real fault lines in how we design AI systems today, what’s actually being built in response to each, and where I think the state of the art still falls short.

I cannot deny that Agentic AI is certainly a big change for the society. My self I’m using on premise Agentic system and Agentic system provided by other companies in my day to day. However, I believe, that beyond having more powerful models behind, we need to tackle with urgency other critical topics. In my opinion three big elephants in the room:

  • AI Safety and privacy. Specially getting extremely complex in the context of agentic with highly distributed computing and data sources.
  • Intelligence and memory. We need to change our metrics to optimize from absolute performance normalized to cost into something that mesures intelligence and memory.
  • Context & Attention. Clearly attention is one of the most important advances over the last few years in the context of Gen AI and context is the fuel that helps make attention specific to user memories and know-how. However, context is finite, context is difficult to share & context is difficult to protect or manage.

Outside from the technical domain, the other question I would like to poke during my next entries is about impact to talent and learning. Certainly, I know what I know thanks to the hard learning curve over years forced by solving complex problems and find ways to get there. How do we do this with coming generations?

In the rest of this post I’m posting some of the thoughts and areas I will develop during next weeks or months. You can also check the slides I presented to ESSERC as an aperitive :).

Denial is a specific failure mode, not a vague one

I don’t mean “denial” rhetorically. I mean something precise: continuing to explore a comfortable subset of the design space while calling it the whole space. It looks like optimising a benchmark that stopped measuring what you care about three years ago. It looks like treating “more GPUs” as a strategy long after it became a grid-interconnection queue. It looks like betting an entire R&D roadmap on one scaling law without asking, seriously, whether it’s still the right bet.

I think the industry is currently doing all three, and I don’t think that’s a controversial claim once you look at the numbers — which is exactly why the rest of this series leans so heavily on sourced, dated data rather than opinion.

Three imperatives, and we’re not clearly winning any of them

Underneath every specific technical problem I’ll cover in this series sits a broader question about what kind of AI industry we’re actually building, and for whom. I’ve found it useful to organise that question around three imperatives.

Figure 1. The three imperatives underlying every fault line in this series.
Figure 1. The three imperatives underlying every fault line in this series.

Resources — energy, compute, capital, materials, and the fabs and packaging lines that turn any of them into working silicon. This is the imperative with the most visible crisis today: demand for AI infrastructure is growing faster than the grids that have to support it. I’ll go deep on this in Part 3.

Talent — the people who design, build, and operate the systems underneath every model. I think this is the most under-discussed of the three. Capital and attention flow overwhelmingly toward model-layer work, while the hardware and systems engineering that makes any of it run at scale is quietly short of people, and getting shorter. Part 8 is dedicated to this.

Progress — using AI to solve larger, more complex problems, without simply assuming that “bigger model” is the only path to get there. I think this imperative has been quietly narrowed into a bet on one scaling law, and that bet deserves more scrutiny than it currently receives. Part 4 makes that case in full.

These three aren’t independent. A Resources shortfall changes what Progress is even achievable, since a power-constrained system can’t simply out-train its way to a better efficiency ratio. A Talent shortfall changes how fast any Resources solution can actually get engineered. And a narrow reading of Progress — chasing scale for its own sake — actively worsens both of the other two, by pulling capital and people toward ever-larger training runs instead of the efficiency and specialisation work I think is at least as urgent.

A useful test for any major architecture or infrastructure decision: which of these three imperatives is it trading against the other two — and was that trade made deliberately, or by default?

What’s coming in this series

Part 2 sets out, in hard numbers, exactly how much changed in the twelve months before this series was written — capability, scale, energy, and a couple of facts about model efficiency that I think are still under-appreciated outside specialist circles. Parts 3 through 6 go through what I’ve come to think of as the four real fault lines in AI system design: Resources (scale and the power wall), Progress (general intelligence vs. intelligence-per-watt), Trust (reliability and the cost of being wrong), and Value (context as AI’s real currency). Part 7 covers the standards question — why I think proprietary interconnects and security stacks are a dead end for anyone who isn’t the single largest incumbent. Part 8 is about talent, which I consider fault line zero. And Part 9 closes the series with something different in kind: a deliberately vendor-neutral sketch of the system I’d build if I were starting from a blank page today.

None of what follows is a product pitch. It’s an attempt to name the walls of the box before we forget we’re standing inside one.

Disclaimer: Yes, I did use a text editor to write this post. AI help to fix grammar and typos. But the context is still mine :)

References

  1. Stanford HAI, *The 2026 AI Index Report*.
  2. International Energy Agency, "Key Questions on Energy and AI", April 2026.
  3. This post is adapted from the keynote "Design Space Exploration or Design Space Denial? The Case for Rethinking Chip-to-System Co-Design in the Agentic Era", delivered at ESSERC 2026 (52nd IEEE European Solid-State Electronics Research Conference), Palma, 10 September 2026, and the accompanying Openchip position paper.
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