~/biography · git log --all
Two decades moving from research, into silicon, into systems
I hold a PhD in Computer Architecture, and I've spent my career on one throughline: making the hardware underneath computing worthy of what runs on it — first as a researcher, then inside one of the industry's largest silicon organisations, and now building sovereign, open silicon of my own.
I started at the Barcelona Supercomputing Center, five years into high-performance computing research — publishing more than sixty papers and mentoring doctoral candidates working on the same problems.
In 2008 I joined Intel, where I spent sixteen years across three roles: seven as a hardware architect in the Product Group, working on CPU architecture, design and performance modeling; six in the Data Center and AI group, moving from chip-level work into platform design, orchestration and power management at system scale; and finally as Senior Principal Engineer and Chief System Architect for Network and Edge in Intel’s CTO Office, leading a global group of architects defining edge-computing architecture across retail, transportation and industrial verticals. Along the way I was named a Top Intel Inventor for five consecutive years, 2019–2023.
In 2024 I founded Openchip, a Barcelona-based company building sovereign, open RISC-V silicon for Europe — production-grade chips for healthcare, finance, HPC and defense, backed in part by €115M in Spanish public investment. It’s the place where the argument I make in this journal gets tested against real silicon.
Career
Web developer and system administrator, RA Interactius
First professional work, alongside undergraduate study.
Intern and simulator developer, Computer Architecture Department, UPC
Data-centre administration and automation frameworks, then design and development of a general-purpose architecture simulator.
Research Scientist, CEPBA–IBM Research Institute
Performance analysis and projection for MPI and OpenMP applications; participation in the HPC-Europa project.
Senior Data Center Research Scientist, Barcelona Supercomputing Center
Cluster and Grid Computing team, leading data-centre orchestration and management policies across the HPC-Europa, XtreemOS, CoreGRID and Mare Incognito projects.
Senior CPU Architect, Product Development Group — Intel
Hardware architect for the Xeon processor family: landing-zone requirements and architecture for on-die protocols across memory, cores and QPI.
Chief System Architect, Innovation and Pathfinding Architecture Group — Intel
Co-design of next-generation computing architectures, from processor to system level, across Intel's European systems.
Chief Technology Officer, Leadership Academy of Barcelona
Leadership training built on the idea of the sustainable executive — driving competitiveness through executive health and wellbeing. Clients included Telefónica, Oracle, Nestlé, Danone and Rabobank.
Data Center Server Platform Architecture EMEA — Intel
Chief architect for Intel Edge, leading server pathfinding architecture and customer engagements across EMEA.
Scientific Advisor, NearbyComputing
Strategic advice on orchestration of distributed systems and the impact of processor, platform and data-centre architecture.
Top Intel Inventor
Awarded to the individual with the most patents filed and granted within the organisation.
Chief System Architect, Network and Edge — Intel CTO Office
Senior Principal Engineer leading a global group of architects across retail, transportation, industrial and network verticals, defining system-level edge architecture and future technology requirements.
Founder & CEO, Openchip
Barcelona-based company building sovereign, open-standard RISC-V silicon for European digital sovereignty.
Strategic MoU with imec
Long-term collaboration on hardware/software co-designed AI systems; Openchip opens an office in Ghent, Belgium.
Partnership with NEC
Co-developing RISC-V vector processing units for NEC's Aurora HPC platform.
Education
PhD in Computer Architecture and Technology
Computer Architecture Department (DAC), Technical University of Catalonia (UPC)
Thesis: "Job-Guided Scheduling Strategies for Multi-Site HPC Infrastructures".
Space Studies Program
International Space University
Attendance supported by the European Space Agency.
Postgraduate Programme in Grid Computing and High Performance Parallel Computing
University of Manchester, UK
Engineering Degree in Computer Science
Barcelona School of Informatics (FIB), Technical University of Catalonia (UPC)
Teaching and supervision
Eleven years lecturing on processor and high-performance architecture alongside the industry work, plus doctoral and master's project supervision.
Associate Professor and Master Project Advisor
Open University of Catalonia (UOC)
Master courses in Operating Systems and Processor Architecture, High Performance Architectures and Advanced Processor Architectures; advisor for final master projects in high-performance computing.
Part-time Assistant Professor
Computer Architecture Department, Technical University of Catalonia (UPC)
Operating Systems undergraduate course, Barcelona School of Informatics.
Lecturer, enterprise and academy courses
UPC Computing Science Center and BIT Computer Science Academy
Search engines, XML technologies, data management and encryption technologies.
Research collaboration on embedded systems and Linux kernel optimisation
With Prof. Marisa Gil, Computer Architecture Department, UPC